PipeCORE PCI-Express and CXL PHY

1-64Gbps PCI-Express Gen6 and CXL PHY

The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe Gen1 – Gen6 PHY, that is capable of also operating at 64Gbps PAM4 PCIe Gen6 rates. It includes a hardened PMA layer and a soft PCS layer deliverable. The PipeCORE is based on the industry leading AlphaCORE DSP architecture.

The PipeCORE is power and performance optimized for the strenuous challenges of PCIe and is targeted to deliver unparalleled bandwidth for the next generation of computing interfaces.

Targeted for 45+dB of channel loss for for PCIe Gen 1 – Gen6 and CXL NRZ and PAM4 rates, the PipeCORE delivers a power-optimized, physical layer IP that yields more than 400Gbps of data throughput per millimeter of Silicon perimeter.

High speed performance

Low power, DSP based architecture provides robust operation over long copper backplanes.

Low power architecture

Low power DSP architectures enables next generation PCIe Gen5 and CXL interfaces. Supports L1 substate power management. Option power gating implemented.

Robust training

Integrated microcontroller per lane enables fast PCI-Express (PCIe) training in both foreground and background adaptation to enable both NRZ and PAM4 rates.

Industry standard support

The PipeCORE PCIe Gen1-6 PCS layer support both PIPE 5.X and PIPE6.0 and has been validated with leading PCIe and CXL Controllers. Support low latency architecture optimal for CXL applications.

SPECIFICATIONS

Receive Equalization

Designed for closed eye, backplane systems up to 45dB of insertion loss at Nyquist for with NEXT for NRZ and 38dB for PAM4 PCIe Gen6. Digital CDR meets strict PCIe Jitter Tolerance IO Density.

Power Optimization

Built for high performance, PipeCORE is capable of delivering equalization for up to 45dB channels, while minimizing power consumption for NRZ and PAM4 rates.

Configurability

Supports 1, 4, 8, 16 lane configurations, different IP options available for north/south versus east-west orientations. PipeCORE also supports multiple rows of stacking for high density switching applications, and can also support multiple different metal options for SOC flexibility.

Devices Used

Standard CMOS digital devices