High speed performance
Low power, DSP based architecture provides robust operation over long copper backplanes.
Low power architecture
Low power DSP architectures enables next generation PCIe Gen5 and CXL interfaces. Supports L1 substate power management. Option power gating implemented.
Integrated microcontroller per lane enables fast PCI-Express (PCIe) training in both foreground and background adaptation to enable both NRZ and PAM4 rates.
Industry standard support
The PipeCORE PCIe Gen1-6 PCS layer support both PIPE 5.X and PIPE6.0 and has been validated with leading PCIe and CXL Controllers. Support low latency architecture optimal for CXL applications.
Designed for closed eye, backplane systems up to 45dB of insertion loss at Nyquist for with NEXT for NRZ and 38dB for PAM4 PCIe Gen6. Digital CDR meets strict PCIe Jitter Tolerance IO Density.
Built for high performance, PipeCORE is capable of delivering equalization for up to 45dB channels, while minimizing power consumption for NRZ and PAM4 rates.
Supports 1, 4, 8, 16 lane configurations, different IP options available for north/south versus east-west orientations. PipeCORE also supports multiple rows of stacking for high density switching applications, and can also support multiple different metal options for SOC flexibility.
Standard CMOS digital devices