This core is our 400G SOC solution to transpond 4x100GE or 400GE client onto Optical Transport Network (OTN). In 4x100GE mode, each lane can be configured independently and clocking and timing are also independent. In 400GE/OTUC4 mode, the OmegaCORE processes the OTUC4 OH bytes in multiplexed fashion. In OTUC4 mode, the GFEC per 100G slice can be disabled or removed if external coherence module or high-gain FEC is used.
Line-Side Mode Support
- 1x400G OTUC4 / ODUC4 (with or without GFEC)
- 2x200G OTUC2 / ODUC2 (with or without GFEC)
- 4x100G OTU4 / ODU4 (with or without GFEC)
Client-Side Mode Support
- 1x400G Ethernet (400GE – IEEE 802.3bs-2017 )
- 4x100G Ethernet (100GE – IEEE 802.3ba with 802.3bj FEC KR4/KP4)
The OTN core of OmegaCORE supports three levels of OH insertions and extractions : register programming, memory programming and external programming through a dedicated OH port. The gFEC function can be disabled (or removed to save area) and a custom high-gain FEC can be used. The OTN core supports full alarm and OH inserts and extracts as specified in ITU G.709 and ITU G.798.
All Alphawave OmegaCORE’s have been tested on both Intel/Altera and Xilinx FPGA hardware. Alphawave partners with leading test equipment vendors like Spirent and Viavi to prove interoperability.
The OmegaCORE family of IPs are designed for eﬃciency. Built-in data buﬀers are eﬃciently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Alphawave IP can provide simulation models and routable RTL along with detailed interface documentation. Contact Alphawave IP for more information.
- 4x100GE (100GBASE-R) to 4x100G OTU4 with GFEC
- 4x100GE (100GBASE-R) to 2x200G OTUC2 with GFEC
- 4x100GE (100GBASE-R) to 400G OTUC4 with GFEC
- 400GE (400GEBASE-R) to 400G OTUC4 with or without 4xGFEC