The OmegaCORE OTN 100G Transponder with AES is a multi-lane SOC solution to transpond 100GE or CBR100G client onto Optical Transport Networks (OTNs). Each lane can be configured independently. Each lane core supports mapping of CBR100G client and 100GE client. For 100GE client, the core can perform Constant Bit Rate (CBR) async mapping using GMP or packet mapping through GFP. With packet mapping, a bandwidth buffer is used for bandwidth management between the GFP mapper and the 100GE MAC.
- OTU4+G.709 GFEC
- OTL4.10 or OTL4.4 (with flexible deskew buffers)
- 100G Ethernet (IEEE 802.3ba + 802.3bj FEC)
- 100G CBR clients
- Higher port density
- Better power efficiency
The OTN core of OmegaCORE supports three levels of OH insertions and extractions : register programming, memory programming and external programming through a dedicated OH port. The gFEC function can be disabled (or removed to save area) and a custom high-gain FEC can be used. The OTN core supports full alarm and OH inserts and extracts as specified in ITU G.709 and ITU G.798.
All Alphawave OmegaCORE’s have been tested on both Intel/Altera and Xilinx FPGA hardware. Alphawave partners with leading test equipment vendors like Spirent and Viavi to prove interoperability.
The OmegaCORE family of IPs are designed for eﬃciency. Built-in data buﬀers are eﬃciently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Alphawave IP can provide simulation models and routable RTL along with detailed interface documentation. Contact Alphawave IP for more information.
The following shows a few examples of how the transponder can be configured for different applications:
100GBASE-R <> CAUI/CAUI4 <> Ethernet Mac <> GFP-F <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
100GBASE-R <> CAUI/CAUI4 PCS-R/MLD <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
100G CBR <> SFI-S <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
Each lane is independent and can be dynamically re-configured to perform a different function without affecting the other lanes in mission.
Our SOC solution can offer much higher lane (port) density per chip, typically 1-4 depending on ASIC/FPGA sizes. As a result of higher port density, better power efficiency and cost effectiveness can be obtained.
- Product Guide
- Functional description
- IO and interface description
- Register Map
- Clocking scheme
- Reset scheme and strategy
- Software bringup procedure
- Integration/User guide
- SDC Timing Constraints
- RTL Netlist
- Standard one year support