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OmegaCORE 1.6T Multi-Protocol Controller

The OmegaCORE Multi-Protocol Controller is a complete MAC/PCS/FEC solution for throughput up to 2x800GE as defined by IEEE802.3 and Ethernet Technology Consortium specifications. It combines Ethernet, FiberChannel, and FlexO/OTN streams at a variety of rates to a single multi-channel core to improve power and area efficiency. It targets ASIC and SOC applications that have high bandwidth and ultra-low power and area requirements by leveraging 112G and 56G SerDes. 

Omegacore 1.6T ZX Multi Protocol Controller Fig 2


The OmegaCORE 1.6T Multi-Protocol Controller (OmegaCORE 1p6T_ZX) from Alphawave IP is a multi-channel, multi-rate Ethernet aggregator that supports tributaries from 800GE to 1GE, utilizing the 112Gbps SerDes and 56Gbps SerDes. The supported ethernet protocols are 800GE, 400GE, 200GE, 100GE, 50GE, 40GE, 25GE, 10GE, 1GE, and 256GFC, 128GFC, 64GFC, 32GFC, 16GFC, 10GFC as well as forward error correction (FEC) framing of FlexO-1/2/4-SR and OTU25/50-RS. It supports any legal combination of Ethernet/Fiberchannel/FlexO rate up to 2x 800G (1.6T). It supports a maximum of 16 or 32 ethernet channels and works most efficiently when coupled with one of Alphawave’s 112G SerDes solutions.

800GE Support

The core supports 800GE which uses a full 800GE MAC and a pair of “bonded” 2 x 400GE Physical Coding Sublayer (PCS).

. The 800GE takes advantage of 112Gbps SerDes and uses virtual logical lanes in a “bonded” 2 x 400GE PCS. This improves power efficiency in 800G operation. The 800GE is compliant to the Ethernet Technology Consortium Standard.

The northbound interface from the multi-channel MAC provides a configurable system interface. The multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SerDes. The core is responsible for channel alignment and FEC (where applicable).

Industry Standard

Latest PHY Standards

Supports the latest PHY standards, utilizing both 112Gbps and 56Gbps SerDes. It's our Gen3 Ethernet/FiberChannel/FlexO solution.


Lowest Latency, Area and Power

Leveraging the latest semiconductor processes, we can achieve core clock frequencies of 800MHz to 1.6GHz


Highly Configurable

Using a highly efficient slice architecture, we can combine multi-channel into a single core. We support an NxM crossbar which allows remapping of all SerDes in both TX and RX directions.


Maximum Bandwidth

OmegaCORE allows access connections supporting 1GE, 10GE, 25GE, 40GE, 50GE, 100GE, 200GE, 400GE, and 800GE in any combination on any port or groups of ports to a maximum total bandwidth of 1.6Tbps



  • Digital crossbar among all SerDes lanes in both TX and RX directions in the SerDes Mux/Demux
  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • Ultralow latency and power-efficient FEC core with support for IEEE 802.3 required FEC variances, including:
     - Low Latency Reed-Soloman Forward Error Correction (LL RS-FEC (272, 258)
     - 4 Lane (x4) Electrical Backplane (KR4 RS-FEC (528,514)
     - Copper Backplane x4 (KP4 RS-FEC (544,514)
     - Twin axial copper / Fibre (FC-FEC (2112,2080)
  • Support all IEEE802.3 PCS, FEC, and MAC statistics and alarms
  • Dynamically change rate on any port without affecting existing traffic
  • Standard ETC 800GE supports with bonded 2 x 400GE PCS and a single 800G MAC

Proven Interoperability

All OmegaCORE’s have been tested on both Intel/Altera and Xilinx FPGA hardware. Alphawave partners with leading test equipment vendors like Spirent and Viavi to prove interoperability.

The OmegaCORE family of IPs are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Alphawave IP can provide simulation models and routable RTL along with detailed interface documentation. Contact Alphawave IP for more information.

Add-on Features

  • HiGig, HiGig+ and HiGig-lite​
  • 1588v2, OAM, OWAMP, TWAMP time stamping 1-step and 2-step​
  • xGFC/FlexE/OTN/FlexO /OTU25/50-RS access port​
  • FC1200 to 256GFC FC2 Monitoring​
  • 802.1Qbb Priority Flow Control (PFC) up to eight priorities​

Additional Variants

Our highly-integrated multi-protocol solutions also come in a few additional variants. You may request our 1.6T option with the form at the bottom of this page. If interested in our other variants, please contact [email protected].

  • OmegaCORE 1p6T ZX/DX/AX 
  • OmegaCORE 800G ZX/DX/AX
  • OmegaCORE 400G ZX/DX/AX
  • OmegaCORE 100G ZX/DX/AX
Chiplet Ips


  • Product Guide
    • Functional description
    • IO and interface description
    • Register Map
    • Clocking scheme
    • Reset scheme and strategy
    • Software bringup procedure
    • Integration/User guide
  • SDC Timing Constraints
  • RTL Netlist
  • Standard 1-year support

Typical Configurations

PCS Channel Type Num Channel(s)
with 16 x 112G SerDes Config
800GBASE-R8 2        
800GBASE-R16 1        
400GBASE-R16 1 X      
400GBASE-R8 2 X      
400GBASE-R4 4 X      
200GBASE-R8  2 X      
200GBASE-R4 4 X      
200GBASE-R2 8 X      
100GBASE-R4 X X   X
100GBASE-R2 8 X      
100GBASE-R1 16 X      
50GBASE-R4 4       X
50GBASE-R2 8 X X    
50GBASE-R1 16 X      
40GBASE-R4 4     X X
25GBASE-R1 16   X X X
10GBASE-R 16     X X
1GBASE-X / SGMII / 100M /10M 16       X