Chiplet Ips

DieCORE XSR MSS

25-112Gbps Short-Reach PHY

The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards.

The DieCORE is a companion IP to the AlphaCORE LR IP, for large datacenter SOCs that are moving to multi-chiplet MCM products based on organic substrates or Silicon interposers. The DieCORE allows signals to be transferred across chiplets with sub-mW/Gbps power consumption, and at an IO density of over 1Tbps per millimeter of Silicon.

Diecore Web 2

Highspeed

High speed performance

DieCORE employs a low noise, high speed analog front end that delivers performance and configurability to support both PAM4 and NRZ signalling.

Power

Low power architecture

DieCORE operates at sub-mW/Gbps power consumption, while still providing robust 8-10dB of equalization for both chiplet and optical interface.

Tracking

Tracking CDR

DieCORE operates with a continuously tracking CDR that provides robust data recovery in large MCMs across process, voltage and temperature.

Industry Standard

Industry standard support

DieCORE eliminates the need for costly proprietary interface solutions by delivering high density low power support for both XSR and USR IEEE and OIF standards.

SPECIFICATIONS

Receive Equalization

DieCORE has been co-optimized to provide robust, low power equalization for die-die applications.

Power Optimization

DieCORE delivers a world-leading 1Tbps of IO density per millimeter of Silicon.

Configurability

Supports 1, 4, 8, 16 lane configurations, different IP options available for north/south versus east/west orientations. DieCORE also supports multiple rows of stacking for ultra-high density chiplet applications, and can also support multiple different metal options for SOC flexibility.

Devices Used

Standard CMOS digital devices

DieCORE XSR MSS IP – Factsheet
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