The AresCORE 16G Die-to-Die (D2D) IP implements a wide-parallel and clock forwarded PHY interface for multichannel interconnections up to 16Gbps. The PHY IP is configurable to support the leading standards in the industry such as BOW (Bunch of Wire), and OHBI (Open High Bandwidth Interface) and UCIe (Universal Chiplet Interconnect Express) providing customers a D2D solution that is compliant with industry standards.
AresCORE16 can be configured to support advanced packaging such as CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated-Fan-Out) for maximum density, and Organic Substrates for most cost-effective solution covering all market segments.
The AresCORE16G D2D IP is an extremely power efficient low-latency interconnect allowing the connection between two dies through short-reach low-loss channels. Our proprietary architecture allows SOC teams to reduce IO complexity and save power.
The AresCORE16G D2D IP can be composed with multiple modules to achieve high density throughput per die shoreline.
The AresCORE16G D2D Master Controller integrates and simplifies training and calibrations, while maintaining product level flexibility.
The AresCORE16G D2D IP is compliant with IEEE 1149.1 (JTAG) and 1149.6 (AC JTAG) boundary scan. The built-in self-test (BIST), internal and external loopback, and Non-Destructive Eye Diagram provide on-chip testability and visibility into channel performance.
Die-to-die interconnects enable SOC developers to break the boundaries of the reticle limit by including multiple dies in the same package. This multi-die approach to silicon design allows for better yielding, smaller purposeful dies vs traditional SOCs. The main target applications of D2D interconnects include, but are not limited to:
- AI accelerators
- Server class CPUs
- Network switches designed for large compute
- 5G base stations
- IO and optical transceivers