High speed performance
ApolloCORE employs a low noise, high speed analog front end that delivers performance and configurability to support both PAM4 and NRZ signalling
Low power architecture
AppolloCORE delivers 40% power savings compared to leading long reach SerDes while still providing robust equalization for MR and VSR channels.
Sub-sampling clock multiplier
ApolloCORE CDR employs a wide tuning, sub-sampling clock multiplier that can track hundreds of ppm frequency error and provide continuous tracking
Designed for MR, VSR, and XSR based systems up to 24dB of insertion loss at Nyquist for PAM4. ApolloCORE includes a blind adaptive receive equalizer.
Built for high performance, ApolloCORE is capable of delivering equalization for up to 24dB MR channels, while consuming less than 3.4mW/Gbps
Supports 1, 4, 8, 16 lane configurations, different IP options available for north/south versus east/west orientations. ApolloCORE also supports multiple rows of stacking for high density applications, and can also support multiple different metal options for SOC flexibility
Standard CMOS digital devices