- Products
- Connectivity IP Cores
- ZeusCORE XLR MSS


Most Likely Sequence Detector (MLSD)
MLSD uses Viterbi Detection to make slicing decisions based on a sequence of data symbols. MLSD minimizes decision error across a sequence of symbols and improves the Signal-to-Noise Ratio and Bit Error Rate of systems.

High speed A/D
The ZeusCORE MSS IP employs a high speed A/D architecture that has configurability for both the A/D sampling rate as well as the A/D resolution

Sub-sampling clock multiplier
The ZeusCORE CDR employs a wide tuning, sub-samplingclock multiplier that can track over 5000ppm error for both scrambled and 8B/10B encoded data

Master controller
The ZeusCORE DSP Master Controller includes:
- All required training is integrated, without the need of external RAM
- Non-destructive eye monitoring
- 1+D Partial Response Coding
ZeusCORE Proven IP
This video demonstrates the ground-breaking performance of the Alphawave ZeusCORE IP.
SPECIFICATIONS
Receive Equalization
Designed for closed eye, backplane systems greated then 40db of insertion loss at Nyquist for PAM4 with high MLSD. Includes blind adaptive equalizer and channel estimator.
Output Driver Voltage
Programmable 400 – 1200 mVdiff-pkpk (inner eye)
Supply Voltages
Core - 0.75V
IO - 1.2V
Devices Used
Core – SVT, LVT and ULVT
IO - 1.8V SVT